Integrated circuits may be formed using photolithography processes with illumination sources having wavelengths more than twice a desired pitch of metal interconnect lines in the integrated circuits. Attaining desired tradeoffs between fabrication costs and fabrication yield may be difficult. For example, standard single photoresist patterns begin to blur at about the 45 nm feature size and 100 nm pitch (feature size plus space between features) when printing with 193 nm wavelength light.
Double patterning technology (DPT), illustrated in FIGS. 1, 2A, 2B, 3A and 3B may be used to print patterns with a pitch (minimum geometry size plus minimum space) that is tighter than can be printed with a single exposure. In DPT technology approximately one half the geometries of the interconnect pattern 20 shown in FIG. 1 are placed on a first double patterning photo mask shown in FIG. 2A and the remainder of the geometries are placed on a second double patterning photo mask shown in FIG. 2B. These photomasks are printed individually on the same level of interconnect to form an interconnect pattern with a much tighter pitch than either of the DPT photomasks. For example, a pattern with 100 nm pitch which prints blurred when all geometries are placed on a single photo mask may be decomposed into two DPT photo masks each with a 200 nm pitch which print without blurring.
Likewise the vial level 26 shown in FIG. 1 may be rendered DPT compatible by drawing approximately half the via geometries on one DPT via reticle as shown in FIG. 3A and drawing the remaining via geometries on a second DPT via reticle as shown in FIG. 3B.
Cell libraries of standard cells are commonly used in the design and layout of integrated circuits. For example, standard cells may be drawn for commonly used logic functions such as NAND and NOR gates or adders and placed in the cell library. Each time this logic function is required the standard cell may be retrieved from the cell library and placed in the circuit. This saves the time and cost of having to relay out the same pattern multiple times.
A problem arises when interconnect and via levels with tight pitch must be DPT compatible. Even though individual standard cells may be laid out to be DPT compatible as in FIG. 1, DPT conflicts may arise when the DPT clean standard cells are placed next to one another in an integrated circuit as is shown in FIG. 4. Four placements, 30, 32, 34, and 36, of the DPT clean cell (FIG. 1) show across cell boundary DPT design rule violations 38 and 40. Vias, 38, violate the same color via space design rule across the cell boundary, and metal-1 geometries 40 also violate the same color space design rule across the standard cell boundary.
A method for drawing DPT compatible standard cells that are free of across border DPT conflicts when placed adjacent to each other in an integrated circuit is desirable.